Split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. The memory cell is shown in FIG. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22b that extends up and over the floating gate 20. The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26. The memory cell is referred to as split gate, because two different gates (floating gate 20 and control gate 22) separately control the conductivity of two different portions of the same channel region 18. Therefore, the channel region 18 can conduct current between the source and drain regions 14/16 only if both of its portions are turned on by the floating and control gates 20/22.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via the well-known technique of Fowler-Nordheim tunneling. Tunneling of electrons from one conductive gate to another conductive gate through intervening insulation is well known and not further described.
The memory cell is programmed (where electrons are placed on the floating gate 20) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. The portion of the channel region 18 under the control gate 22 is turned on (made conductive) by the positive voltage on the control gate 22. The portion of the channel region 18 under the floating gate 20 is turned on (made conductive) by the positive voltages on the control gate 22 and drain region 16 being capacitively coupled to the floating gate 20. Electron current will flow starting from the source 14 towards the drain 16 in the portion of the channel region 18 under the control gate 22. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 and onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. This programming technique is well known as hot-electron injection, and is commonly used especially for split gate memory cells.
The memory cell 10 is read by placing positive read voltages on the drain region 16 and control gate 22 (which turns on the portion of channel region 18 under the control gate 22). If the floating gate 20 is positively charged (i.e. erased of electrons), then the portion of the channel region under the floating gate 20 is turned on as well (because of the capacitive coupling of the positive voltages to the floating gate 20), and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off (because the capacitive coupling of the positive voltages cannot overcome the negative charge on the floating gate 20), and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state. Those skilled in the art understand that the terms source and drain can be interchangeable, where the floating gate 20 can extend partially over the source 14 instead of the drain 16, as shown in FIG. 2.
Split gate memory cells having more than two gates are also known. For example, U.S. Pat. No. 8,711,636 (“the '636 patent”), incorporated herein by reference, discloses a split gate memory cell with an additional coupling gate disposed over and insulated from the source region, for better capacitive coupling to the floating gate. See for example FIG. 3 showing a split gate memory cell with a coupling gate 24 disposed over source region 14.
A split gate memory cell having four gates is disclosed in U.S. Pat. Nos. 6,747,310 and 7,868,375, which are incorporated herein by reference. For example, as shown in FIG. 4, the four gate memory cell 10 has a source region 14, a drain region 16, a floating gate 20 over a first portion of channel region 18, a select gate 28 over a second portion of the channel region 18 (also referred to as the word line gate), a control gate 22 over the floating gate 20, and an erase gate 30 over the source region 14. Erasing is shown in FIG. 4 by electrons tunneling from the floating gate 20 to the erase gate 30 by placing a high positive voltage on the erase gate 30. Programming is shown in FIG. 4 by heated electrons from the channel region 18 injecting themselves onto the floating gate 20 by hot-electron injection. Below in Table 1 are exemplary voltages and current that can be used to program the memory cells:
TABLE 1SG 28Drain 16Source 14EG 30CG 22Program1 V~1 μA4.5 V4.5 V10.5 V
One issue with hot-electron injection programming is that it requires a significant amount of electrical current for each memory cell to implement. However, programming is often byte-by-byte, which means the memory device must include voltage and current sources sufficiently large enough to provide the necessary voltages and currents for concurrent programming of multiple memory cells. Mass programming using one or more internal charge pumps is difficult because of the high programming current requirements of hot-electron injection. Some parallelization in programming can be achieved using external voltage source(s). However, mass programming is simply not effective for most applications given the high current required, in additional to other factors such as the source line voltage drop. Another issue with hot-electron injection programming is that it takes a relatively long time to complete, given that only some of the electrons traveling from the drain region 16 to the source region 14 end up being injected onto the floating gate 20. The rest complete their journey to the source region 14 without being injected onto the floating gate 20. Therefore, its efficiency in that respect is relatively low.
There is a need for a more efficient technique of programming split gate memory cells having four gates.